8-bit Up/Down Counter using VHDL
The following code is a 8-bit counter with the following settings:
- asynchronous set (set count to the last digit of student ID;
- syncchronous clear( set count to 0)
- enable (stop counting)
-- Student ID: 123456789
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY eight_bit_counter IS
PORT(clk, clear, set, enable : IN STD_LOGIC;
count : OUT INTEGER RANGE 0 TO 127);
END eight_bit_counter;
ARCHITECTURE behavior OF eight_bit_counter IS
BEGIN
PROCESS(clk, clear, set, enable)
VARIABLE cnt : INTEGER RANGE 0 TO 127 :=89; – set cnt range to 7 bits and initialize it to 89
VARIABLE direction : INTEGER RANGE -1 TO 1:= -1; – flag to control up/down direction
BEGIN
IF(set = ‘1′) THEN –check the set input
cnt := 89;
direction := -1;
ELSIF(clk’EVENT AND clk =’1′) THEN
IF(clear = ‘1′) THEN — check if the input clear is high
cnt := 0;
direction := 1;
END IF;
IF(enable = ‘1′) THEN – check if it is enable
cnt := cnt + direction;
IF(cnt = 89) THEN — if it reaches 89 begin countdown
direction := -1; — set direction to negative to count backwards
ELSIF(cnt = 67) THEN — if it reaches 67 begin counting up
direction := 1; — set direction to positive to count foward
END IF;
ELSE
cnt := cnt; – if the counter is disable just display the last value and stop counting
END IF; – if the counter is enable resume last counting
END IF;
count <= cnt; – out put the cnt to the count
END PROCESS;
END behavior;
